This invention relates generally to high-capacity data switches. In particular, the invention relates to a self-configuring distributed packet switch with an agile optical core that adapts to variations in data traffic loads in a switched data network, and has a large switching capacity.
The volume of data now exchanged through telecommunications networks requires data networks having a large capacity for data transfer. Such networks must also serve large geographical areas. Network scalability to achieve a very large capacity and wide-area coverage may be achieved by increasing the number of nodes in a network and/or increasing the transfer capacity per node. For a given link capacity, e.g., 10 Gb/s, increasing the capacity per node necessitates increasing the number of links per node. In a balanced network, the mean number of hops per node pair is inversely proportional to the number of links per node. Decreasing the mean number of hops per node pair dramatically reduces network-control complexity, facilitates routing functions, and enables network-wide quality of service (QOS) objectives.
Very high-capacity switches are required in order to decrease the number of hops per node pair in a network. Consequently, methods for constructing very high-capacity switches are desirable. It is also desirable to distribute such switches to permit switch access modules to be located in proximity of data traffic sources.
Advances in optical switching technology have greatly facilitated the construction of high-capacity switches using optical space switches in the switch core. The principal problem encountered in constructing high-capacity switches, however, is the complexity of coordinating the transfer of data between ingress and egress, while permitting the creation of new paths between the ingress and the egress as traffic patterns fluctuate. Consequently, there exists a need for a method of increasing data transfer capacity while simplifying data transfer control in a high-speed data switch.
The design of data switching systems has been extensively reported in the literature. Several design alternatives have been described. Switches of moderate capacity are preferably based on a common-buffer design. For higher capacity switches, the buffer-space-buffer switch and the linked-buffers switch have gained widespread acceptance. A switch based on an optical space-switched core is described in U.S. Pat. No. 5,475,679, which issued on Dec. 12, 1995 to Munter. An optical-core switching system is described in U.S. Pat. No. 5,575,320, which issued May 19, 1998 to Watanabe et al.
A buffer-space-buffer switch, also called a space-core switch, typically consists of a memoryless fabric connecting a number of ingress modules to a number of egress modules. The ingress and egress modules are usually physically paired, and an ingress/egress module pair often shares a common payload memory. An ingress/egress module pair that shares a common payload memory is hereafter referred to as an edge module. The memoryless fabric is preferably adapted to permit reconfiguration of the inlet-outlet paths within a predefined transient time. The memoryless core is completely unaware of the content of data streams that it switches. The core reconfiguration is effected by either a centralized or a distributed controller in response to spatial and temporal fluctuations in the traffic loads at the ingress modules.
The linked-buffers switch includes sets of electronic ingress modules, middle modules, and egress modules, and has been described extensively in the prior art. Each module is adapted to store data packets and forward the data packets toward their respective destinations. The module-sets are connected in parallel using internal links of fixed capacity.
A disadvantage of the switching architectures described above is their limited scalability. A scalable switch architecture with an optical core is described in Applicant""s co-pending United States Patent Application entitled SELF-CONFIGURING DISTRIBUTED SWITCH which was filed on Apr. 6, 1999 and assigned Ser. No. 09/286,431, the specification of which is incorporated herein by reference.
While the self-configuring packet switch described in Applicant""s co-pending application represents a significant advance in high speed switching technology, because of the currently available switching speeds of known optical switches, tandem switching is required to adapt the switch to data traffic fluctuations. The disadvantages of tandem switching with respect to control complexity and inefficient use of resources are well known. There therefore exists a need for an agile optical-core distributed packet switch that can rapidly adapt to fluctuations in data traffic loads so that reliance on tandem switch paths is reduced.
Packet transfer delay between an ingress edge module and an egress edge module in a distributed switch includes a propagation delay and a queuing delay at the ingress edge module. The core modules are memoryless and, hence, do not contribute to the packet transfer delay. However, the delay in space-switching a connection in the core requires that the ingress edge modules using a switched connection pause for a predetermined time interval before transferring data over the switched connection. If the space-switching delay is relatively long, being for example of the order of a millisecond, then an affected ingress edge module operating at a high speed may have to buffer a large amount of data during each core reconfiguration interval.
There therefore exists a need for a method of overcoming the switching latency problem without having to provision edge modules with very large buffer capacity.
It is an object of the invention to provide a very high-capacity switch with a channel-switching core having multiple independent optical switching core modules.
It is another object of the invention to provide a method of reconfiguring the core of a packet switch having distributed edge modules and distributed optical switching core modules.
It is yet another object of the invention to provide a self-configuring switch with optical switching core modules that adjusts its internal inter-module connections in response to fluctuations in data traffic volumes.
It is yet a further object of the invention to provide a data switch with an optical switching modular core in which channel switching and connection routing are fully coordinated.
It is another object of the invention to develop a self-configuring switch with a distributed optical switching core that circumvents core-switching latency.
The invention therefore provides an agile optical-core distributed packet switch, comprising a plurality of slow-switching core modules, each of the core modules including a plurality of optical space switches. The core modules are connected to a plurality of fast-switching edge modules by a number of inner channels. The fast-switching edge modules are also connected to subtending packet sources and subtending packet sinks by a number of outer channels. A controller is associated with each core module. The controller instructs the fast-switching edge modules to switch from unused inner channels to respective new inner channels reconfigured in the core module, thereby masking switching latency of the slow-switching core modules without interrupting data transfer from the source edge-modules.
The invention further provides a method of channel switching data packet streams received on inner links from fast-switching edge modules using optical space switches in a core module of a geographically distributed packet switch. The method comprises the steps of using uncommitted connections in the optical space switches to configure new connections in the optical space switches in response to reconfiguration requests received from the fast-switching edge modules, and instructing the fast-switching edge modules to switch from unused inner channels to the new connections reconfigured in the core module, without interrupting data transfer from the source edge-modules.
The core is reconfigured in response to reconfiguration requests sent from the edge modules. The reconfiguration requests are based on data traffic volumes.
The steps of reconfiguration include:
(1) traffic monitoring at ingress edge modules;
(2) communication of traffic data to core modules;
(3) selecting the space switches from which unused connections are to be released and the space switches through which new connections are to be established;
(4) timing the rearrangement of the space switches and source-module links; and
(5) reconfiguration at the ingress edge modules according to instructions received from core module controllers.
Each ingress edge module monitors its spatial traffic distribution and determines its capacity requirement to each egress edge module, each connection being defined in units of a full channel capacity. The channel capacity is indivisible. An ingress edge module generates a table that indicates the preferred core module for a channel to each egress edge module. The method of generating the table is based on topology information. An edge module selects a preferred core module and communicates with the selected core module to request the ingress/egress capacity reallocation. Each core module aggregates all the connectivity-change requests from all ingress edge modules and periodically implements a reconfiguration procedure. The outcome of such a procedure is a list of new connections for one or more of its space switches. Entries in the list that correspond to each ingress edge module are communicated accordingly. The edge modules perform their own reconfiguration procedure, when required. The timing coordination among the ingress edge modules and the core modules is governed by a scheme described in Applicant""s co-pending U.S. patent application Ser. No. 09/286,431, which is incorporated by reference.
In order to distribute the computational effort at the edge modules, the core modules stagger their reconfiguration implementation so that only one of the core modules is reconfigured at a time. The core modules reconfigure in a round robin discipline. A sufficient time period is allowed for each reconfiguration. Once a core module has completed its reconfiguration task, if any, it sends a message to a next core module permitting it to proceed with the reconfiguration process. Such a message is not required if a core module uses its full reconfiguration-time allocation. The timing process is preferably enabled by the collocation of a selected edge module with each core module.